Frame Timing Detection Circuit for Character Code Broadcasting System (Patent No.4819231(U.S.), Patent No.1222558(Canada), Patent No.42090(Korea)) Decoding circuit in accordance with the present invention This patent relates to a framing synchronized reproduction system for the transmission of multiplexed, coded-character graphic information using vertical blanking periods in TV signals or with other methods. The framing synchronizer indicates divisions of character code and the framing synchronized reproduction system in order to reproduce the coded characters at the receiver. Conventionally, a framing code extraction circuit has been employed for this purpose. This circuit extracts the frame timing value by setting the distance between the clock-run-in signal and the framing code to be three or greater and then shifting the code to detect the distance. However, this circuit was not robust versus framing code errors caused by noise in the digital transmission channel. This patent system provides a frame timing detection circuit capable of reliable timing reproduction by using data error correction and eliminates the need for the framing code extraction circuit. The transmitter uses error correction-coded 34-byte (190-bit data signals, 82-bit parity information) data, which follows the one byte clock-run-in signal and one byte framing code with an exclusive-OR operation between a 28-1=255-bit M-sequence PN signal. The receiver sends 36-bytes of data, including the 34-byte data signal described above, to the CPU. The CPU then executes an exclusive-OR with the PN signal, using the first byte as a framing code, and feeds the following 34-bytes to the error correction circuit. Inaccurate frame timing results in errors in more than half of the 34 bytes, for which error correction cannot be completed. Based on such an improbable error rate, the system determines that the frame timing is inaccurate and proceeds with another error correction attempt using a frame timing that is shifted one bit from the previous timing. This attempt is repeated a maximum of 16 times, or until proper error correction occurs. Error correction performed at a correct timing will not detect any errors in a packet, except for errors caused in the transmission channel. Therefore, if error correction can be completed, the system accepts the frame timing as correct. It then sets the number of shifts and proceeds to the next process. The figure shows the flowchart of the patent system's operation.