Transmission Scheme with Multi-Level Coded Modulation
KOIZUMI Yuki, SUZUKI Yoichi and KOJIMA Masaaki
ABSTRACT
NHK has been studying a multi-level coded modulation scheme for expanding satellite transmission capacity. It can bring out the transmission performance of multi-level modulation scheme by designing the constellation, bit allocation, and error correction codes in an appropriate combination. We designed SP (Set Partitioning)-64APSK (Amplitude Phase Shift Keying) with a coding rate of 4/5 as a multi-level modulation scheme beyond 32APSK supported by the ISDB-S3 (Integrated Services Digital Broadcasting for Satellite, 3rd Generation) transmission scheme for satellite broadcasting of 4K/8K ultra-high definition television. This paper describes the design of the SP-64APSK coded modulation and shows computer simulation results of its transmission performance.
1. Introduction
Satellite broadcasting of 4K/8K ultra-high definition television (UHDTV) was launched in Japan in December 2018. ISDB-S31) 2) is adopted as the transmission system achieving a transmission capacity of 100 Mbps per transponder (bandwidth of 34.5 MHz), which enables the broadcasting of three 4K programs or one 8K program.
At NHK Science & Technology Research Laboratories (STRL), we have been studying a multi-level coded modulation scheme3) applying set partitioning (SP) (described below) with the aim of expanding transmission capacity in satellite broadcasting4)5)6)7). Multi-level coded modulation applying SP is a transmission scheme that can improve transmission performance by appropriately combining the design of the constellation, bit allocation, and error-correction codes. We designed 64 Amplitude Phase Shift Keying (APSK) coded modulation applying set partitioning (SP-64APSK) with a coding rate of 4/5 to achieve a multi-level modulation scheme beyond the 32APSK scheme supported by ISDB-S3.
In this paper, we present a SP-64APSK coded modulation design method consisting of design methods for the constellation, bit-allocation, and error correction codes on the basis of channel capacity. We also show that transmission performance is improved compared with conventional modulation schemes with Gray mapping*1.
2. Overview of Coded Modulation
This section presents an overview of SP-coded modulation.
SP is a technique that expands the minimum Euclidean distance (Dmin) by dividing each symbol*2 in accordance with the decoding results for each bit (0 or 1). Coded modulation is a modulation scheme that takes into account the capability of error-correction. It improves noise immunity by applying error correction codes with an appropriate capability in accordance with the expansion of Dmin with SP.
To provide an overview of SP-multi-level coded modulation, the decoding process of SP-8 Phase Shift Keying (8PSK) coded modulation is taken as an example (Fig. 1). Three-bit (a1, a2, a3) allocated to the 8PSK constellation is SP-applicable bit mapping, where a1 and a3 are the most significant bit (MSB) and least significant bit (LSB), respectively. SP-8PSK coded modulation signals are decoded in the order of a1, a2, and a3 by a multi-stage decoding process. First, a1 is decoded in the 8PSK constellation, then 8PSK constellation is divided into two Quadrature Phase Shift Keying (QPSK) constellations in accordance with decoded a1 (Dec_a1 of 0 or 1). Next, a2 is decoded in the two QPSK constellations, then, in the same manner, QPSK constellations are divided into four Binary Phase Shift Keying (BPSK) constellation in accordance with Dec_a2 of 0 or 1. Finally, a3 is decoded into the four BPSK constellations. As the decoding stage progresses, robustness against bit errors increases due to the increase in Dmin. This means that the overall transmission performance of SP-8PSK coded modulation is improved by applying an error correction code with a capability fitting the robustness of each bit.
3. Design of 64APSK Coded Modulation
3.1 Definition of Channel Capacity
The 64APSK constellation and SP-applicable bit allocation are designed on the basis of channel capacity T8) in additive white Gaussian noise (AWGN). T is the maximum information transmission rate per unit frequency (bps/Hz).
T8) is defined by Eq. (1) using transmitted symbol x, received symbol y, modulation multi-level number M, and transition probability density function p(y|x). Here, p(y|x) is the conditional probability distribution in which the received symbol is identified as y when x has been transmitted. It has a normal distribution with mean of 0 and variance σ.
The first term of Eq. (1) is the average amount of information in received symbol y. In this design, M is set to 64. The second term represents the conditional entropy of whether y is correctly recognized as x or other symbols when x has been transmitted, which is determined by the carrier-to-noise ratio (C/N) (function of AWGN power σ2) and transmitted symbol x. When M and the received carrier-to-noise ratio (C/N) is fixed, that is, when σ2 is set to a fixed value, T is regarded as a function of x. Therefore, by designing 64APSK constellation and SP-applicable bit allocation so that T is maximized, Dmin is expanded thereby bringing out the transmission performance of SP-64APSK coded modulation.
3.2 Constellation design
This section describes our design method of 64APSK constellation using T as the design criterion. Since the general constellation of APSK modulation is configured to place symbols on multiple concentric circles, it cannot be uniquely determined how the constellation symbols should be arranged on the IQ plane, unlike Quadrature Amplitude Modulation (QAM) with a square lattice constellation. We thus designed a 64APSK constellation by determining design parameters a) – c) listed below (Fig. 2) such that T was maximized under design conditions (1) – (5).
Design conditions:
(1) Constellation symbols are placed on each of all four circles at equivalent intervals.
The circles are defined as the 1st, 2nd, 3rd, and 4th circle in order of increasing radii.
(2) The number of constellation symbols placed on each circle is even.
(3) The average power shall be 1 (normalized power).
(4) Coding rate of 4/5
The coding rate shall be set so as to exceed the transmission bit rate with 32APSK at the practical received C/N when it is applied to 64APSK.
(5) Design C/N is 16 dB.
Design parameters:
a) Number of constellation symbols placed on each circle (p1–p4).
The number of constellation symbols placed on the 1st, 2nd, 3rd, and 4th circle are defined as p1–p4
(∑4i=1pi=64).
b) Constellation symbol phases (θ1–θ4)
Phase between I-axis and the constellation symbols closest to the I-axis are defined as θ1–θ4.
c) Radius ratios between circles (γ1–γ3)
Radii of the 1st to 4th circles are r1–r4. Radius ratios are defined as
γ1=r2/r1, γ2=r3/r1, γ3=r4/r1.
Design condition (5) (design C/N is 16 dB) was determined so that error-free transmission can be achieved at a C/N with a margin of about 1 dB from the theoretical limit C/N*3 of 14.9 dB for DVB-S2X’s9) 64APSK modulation (64APSK (DVB-S2X)) with coding rate of 4/5.
Table 1 lists design parameters a) to c) determined so that T is maximized and the value of T. The values for the 64APSK (DVB-S2X) are also listed in the table for comparison. In addition, the constellations of our 64APSK and 64APSK (DVB-S2X) are shown in Fig. 3 (a) and (b), respectively. As shown in Table 1, the T of our 64APSK constellation achieved 5.0839 bps/Hz, which is larger than that of DVB-S2X.
| Our 64APSK | 64APSK (DVB-S2X) | |
|---|---|---|
| T (bps/Hz) | 5.0839 | 5.0806 |
| Number of constellation symbols (p1–p4) | (12, 16, 18, 18) | (8, 16, 20, 20) |
| Phase (θ1–θ4) (deg) | θ1=15, θ2=22.25, θ3=20, θ4=10 | θ1=22.5, θ2=11.25, θ3=9.0, θ4=9.0 |
| Radius ratio (γ1–γ3) | γ1=2.00, γ2=2.93, γ3=4.05 | γ1=2.2, γ2=3.6, γ3=5.2 |
3.3 Bit allocation and error correction codes
We designed SP-applicable bit allocation to our 64APSK constellation and error correction codes6) 10). As described below, it is possible to design an SP-64APSK coded modulation with high noise immunity by designing an appropriate combination of bit allocation and error-correction codes.
Let the six-bit allocation to our 64APSK constellation be (a1 (MSB), a2 a3, a4, a5, a6 (LSB)). Since the received SP-64APSK coded modulation signals are divided into 32APSK, 16APSK, …, and BPSK in accordance with the decoding results of the previous bits, overall transmission performance with high noise immunity can be achieved by performing bit allocation so that the constellations on each dividing stage should also have as large a T as possible.
The error-correction codes are concatenated codes composed of Low Density Parity Check (LDPC) code11) (inner code) and Bose-Chaudhuri-Hocqenghem (BCH) code (outer code). The LDPC code is an irregular LDPC code*4 with a code length of 44,880 bits having a parity check matrix structure (Low-Density Generator-Matrix (LDGM) structure*5) the same as that in ISDB-S3. The BCH code is a shortened BCH (65535, 65167) code (capable of correcting 23 bits per code word).
There are 64! (≈1×1089) patterns for allocating a six-bit sequence (a1, a2, …, a6) to each of the 64 symbols, which makes it unpractical to calculate T for all patterns and find the pattern with the largest T. We therefore propose a method for efficient bit allocation to our 64APSK constellation. The proposed method is illustrated in Fig. 4 using a1 as an example.
Step 1: Bits of 0 or 1 are alternately assigned to each our circles independently. This enables even dispersal of symbols after division and expansion of the Euclidean distance between symbols. There are 24=16 allocation patterns.
Step 2: 64APSK constellation is divided into 32APSK constellations in accordance with the assigned a1 of 0 or 1, then T with 32APSK is calculated for the 16 allocation patterns. The design C/N is set to 16 dB. Here, since the Ts for a constellation after division for a1 of 0 and 1 are different, the constellation with smaller T is taken for each pattern.
Step 3: The bit-allocation pattern for a1 with the largest T in the 16 patterns is determined. Repeat steps 1 to 3 for determining the bit allocation for a2 to a6 in the same manner. Let the bit allocation designed in steps 1 to 3 be (a1’, a2’, a3’, a4’, a5’, a6’).
Figure 5 shows C/N versus bit error rate (BER) characteristics for each bit a1’–a6’ (before error correction) and Table 2 lists BER of each bit for C/N of 16 dB. The BER for each bit was calculated without error correction by the same system as the computer simulation described below.
As shown in Fig. 5, it is necessary to apply LDPC code with high capability of a low coding rate to the bit whose BER before error-correction is greatly deteriorated such as a1. However, LDPC codes with low coding rate have very long parity bits thereby increasing the percentage of LDGM having a step matrix, which makes the design of LDPC code with randomness*6 difficult. On the other hand, it is desirable to apply LDPC code with a high coding rate that shortens parity bits as much as possible to the bit whose BER before error-correction is low to improve transmission efficiency. However, a high coding rate makes it difficult to design the LDPC codes with a sparse parity check matrix structure, which also makes it difficult to bring out good error-correction performance that suppresses the error floor12). We set the BER range for LDPC code design to 1.5×10-1–2.0×10-3 with the aim of achieving both the randomness and the high error-correction capability of LDPC codes. In Table 2, a1’ and a5’ lie outside this BER range. As for a6’, the BER before error correction is less than BER of 1.2×10-4, which means error-free transmission can be achieved by only BCH code (outer code) making the LDPC code unnecessary.
We therefore shifted the bit position of a1’to a5’ so that the BER of a1 to a5 would fall into the range of 1.5×10-1–2.0×10-3. Specifically, we shifted the bit position of a1’ and a2’ and that of a3’, a4’, and a5’ to obtain a bit allocation of (a1, a2, a3, a4, a5, a6) = (a2’, a1’, a4’, a5’, a3’, a6’). The C/N versus BER characteristics before error correction for this bit allocation are shown in Fig. 6 and BER for each bit at C/N of 16 dB and the LDPC coding rate applied to each bit are listed in Table 3. The BER of a1’ changed from 1.96×10-1 to 1.13×10-1 thereby falling into the range of 1.5×10-1–2.0×10-3. The BER of a2’ degraded from 7.18×10-2 to 1.39×10-1 but nevertheless remained in the range of 1.5×10-1–2.0×10-3. In a similar manner, the BER of a3’, a4’, and a5’ fell into the range of 1.5×10-1–2.0×10-3. The LDPC coding rates in Table 3 were determined on the basis of BER for each bit at C/N of 16 dB.
The frame structure (compliant to ISDB-S3) for each bit designed on the basis of Table 3 is shown in Fig. 7. Ra1 to Ra6 denotes the LDPC coding rate.
The final bit allocation and constellation partitioning results are shown in Fig. 8. The six bits allocated to each symbol are denoted in octal notation (for example, 26 = 010:110).
| BER (C/N=16dB) | |
|---|---|
| a1’ | 1.96×10–1 |
| a2’ | 7.18×10–2 |
| a3’ | 1.86×10–2 |
| a4’ | 8.06×10–3 |
| a5’ | 2.17×10–4 |
| a6’ | 2.67×10–7 |
| BER (C/N=16dB) | LDPC coding rate | |
|---|---|---|
| a1 (a2’) | 1.39×10–1 | 55/120 |
| a2 (a1’) | 1.13×10–1 | 65/120 |
| a3 (a4’) | 1.93×10–2 | 105/120 |
| a4 (a5’) | 4.57×10–3 | 114/120 |
| a5 (a3’) | 2.84×10–3 | 117/120 |
4. Performance Evaluation by Computer Simulation
We evaluated the transmission performance of our SP-64APSK coded modulation under AWGN by the computer simulation system shown in Fig. 9.
On the transmitter side, a transmitting bit sequence is input into the error-correction coding section in the order of a1, a2, …, a6 in accordance with the number of information bits shown in Fig. 7.
Next, a1, a2, …, a6 are extracted from each frame after error correction coding and mapped to the 64APSK constellation according to Fig. 8. Finally, 64APSK transmission signals are obtained with orthogonal modulation on the basis of the amplitude and phase of the symbols after mapping, and C/N is set by adding AWGN to the transmission signals.
On the receiver side, a1, a2, …, and a6 are decoded in the constellation which is obtained by dividing the received constellation in accordance with the decoding results of the previous bits. BER is then obtained by comparing the decoded bit sequence with the transmitting bit sequence. The maximum number of iterations*7 of LDPC decoding is set to 50.
Figure 10 shows the results of computer simulation for C/N versus BER characteristics of our SP-64APSK coded modulation with coding rate of 4/5. The BER characteristics of 64APSK (DVB-S2X) with the same coding rate are also shown in the figure for comparison. To eliminate the effect of the difference in the error-correction codes on performance evaluation, the same LDPC code compliant with ISDB-S3 was applied to both 64APSKs. The BERs were calculated in the range of 10-8 to 10-10, and the C/N at BER of 1×10-11, which is defined as required C/N, was obtained by linear extrapolation as described in ARIB STD-B442). The required C/N of our SP-64APSK coded modulation is 15.70 dB, which is 0.36 dB lower than that of 64APSK (DVB-S2X) with required C/N of 16.06 dB. This result shows that our SP-64APSK coded modulation achieves transmission performance beyond that of conventional 64APSK modulation schemes with Gray mapping.
5. Conclusion
In this paper, we described the design method of SP-64APSK coded modulation on the basis of channel capacity T with the aim of expanding transmission capacity in satellite broadcasting. We designed 64APSK constellation and SP-applicable bit allocation so that T is maximized, then designed error correction codes with a level of capability based on the BER characteristics of each bit. The results of computer simulation found that our SP-64APSK coded modulation achieved highly robust transmission in AWGN compared with the conventional 64APSK with Gray mapping.
In future work, we plan to evaluate the transmission performance of a prototype modem13) equipped with our SP-64APSK coded modulation.
This paper is a supplementation and revision of the following paper published in IEICE Technical Report. Y. Koizumi, Y. Suzuki, M. Kojima, K. Saito and S. Tanaka: “A Study on 64APSK Coded Modulation,” IEICE Technical Report, Vol. 116, No. 243, SAT2016-55, pp. 51-56 (2016)